Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Don't-Care Identification on Specific Bits of Test Patterns
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Low power Illinois scan architecture for simultaneous power and test data volume reduction
Proceedings of the conference on Design, automation and test in Europe
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test relaxation technique for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Reducing IR-drop in the test cycle during at-speed scan testing has become mandatory for avoiding test-induced yield loss. An efficient approach for this purpose is post-ATPG test modification based on X-identification and X-filling since it causes no circuit/clock design change and no test vector count inflation. However, applying this approach to test compression has been considered challenging due to the limited availability of X-bits. This paper solves this serious problem by proposing a novel and practical CA (Compression-Aware) test modification scheme for reducing IR-drop in the widely-used broadcast-scan based test compression environment. This unique scheme features (1) CA circuit remodeling for minimizing the effort of applying test modification to broadcast-scan-based test compression, (2) CA X-identification for increasing X-bits for risky test vectors, and (3) CA X-filling for effectively using limited X-bits in reducing IR-drop. As a result, the CA test modification scheme can achieve significant IR-drop reduction even when a test cube only has a small number of X-bits. This advantage is clearly demonstrated by experimental results on three compression configurations created from an industrial circuit.