System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 2009 International Conference on Computer-Aided Design
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This paper presents a decompression architecture using a periodically alterable MUXs decompressor for scan data volume reduction. Compared to static XOR network, the periodically alterable MUXs decompressor has multiple configurations to decode the input information more efficiently. Three different DFT techniques are proposed to handle hard, firm and soft cores, respectively. With the proposed pattern decompression algorithms and scan decompression architecture, smaller test data volume and test application time can be achieved as compared to previous techniques.