CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Extreme-Voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability Enhancement
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Early Failure Rate screening techniques using automatic test equipment provide a cost effective alternative to manufacturing Burn-In. In this investigation a gate array based test vehicle containing 140,000 used gates was fabricated using early versions of a 0.5 micron 3.3 volt technology. Effectiveness of techniques was evaluated using one fabrication lot containing predominantly gate oxide defects and another one containing predominantly via and particle defects. The screen became more effective as the stress voltage was increased from 4.7 V to 5.0 V. The high voltage stress accelerated time dependent breakdown of weak gate oxide (TDDB). A screen employing voltage acceleration with IDDQ pattern followed by IDDQ test was more effective than the one using functional test vectors. The IDDQ test extended the fault coverage of a functional vector set. Stressing with the IDDQ vector set offered better control over the stress duration and uniformity. It also allowed a generic stress time specification which was independent of the size or function of an individual ASIC design.