CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Evaluation of Early Failure Screening Methods
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
SHOrt Voltage Elevation (SHOVE) Testing
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
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Extreme-voltage screening has been successfullyimplemented to enhance gate-oxide reliability of digitalCMOS ICs. However, the success has not yet beenextended to its analog counterparts. As a result, almost allthe manufacturers employ the digital circuit screeningprocess for the analog modules in mixed-signal CMOSICs. Our pervious study had addressed the issues on howto properly stress analog circuits to enhance the gate-oxidereliability of mixed-signal CMOS integratedcircuits, and the trade-off between the stress coverage andstress time. This paper presents two algorithms thatgenerate a set of stress vectors for an analog circuit (1) tomeet the stress coverage requirement and to result in aminimum stress time; and (2) to meet the stress timerequirement and to result in a maximum stress coverage.