High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement

Authors:
Mohammad Athar Khalil;Chin-Long Wey
Affiliations:
-;-
Venue:
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Year:
2001

Citing 0
Cited 2

Extreme-Voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability Enhancement

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement

Proceedings of the 14th ACM Great Lakes symposium on VLSI

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Abstract

This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost. The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time.