Logic optimization by an improved sequential redundancy addition and removal techniques

BDD-based testability estimation of VHDL designs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis

Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal

IEEE Transactions on Computers

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks

Formal Methods in System Design

Wire reconnections based on implication flow graph

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Binary time-frame expansion

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability

EDTC '96 Proceedings of the 1996 European conference on Design and Test