A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Computers and Electrical Engineering
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Since gaining popularity in the late 1990s, the term "scan compression" has maintained a solid hold within the IC test lexicon. In recent years, however, this technology has taken the test industry by storm. As the cost of test increased to previously unseen heights, some companies complained that the cost to test a single transistor was nearly equal to the cost of manufacturing it. Scan compression technology, however, proved to be a powerful antidote to this problem, as it catalyzed reductions in test data volume and test application time of up to 100x. As a result, the cost of test may well be contained for many years to come. This article sketches a brief history of test technology research that has led to the stunning success of scan compression. This article is not intended to attribute inventors for innovations on a fine-grained timeline. The important concepts of technologies are presented at the high level on a coarse timeline.