Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
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This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST, are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.