On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first time, the applicability of functional self-testing on bus-based symmetric multiprocessors (SMP) and the exploitation of SMPs parallelism during testing. We focus on the impact of the memory system architecture and the cache coherency mechanisms on the execution of self-test programs on the processor cores. We propose a generic self-test routines scheduling algorithm aiming at the reduction of the total test application time for the SMP by reducing both bus contention and data cache coherency invalidation. We demonstrate the proposed solutions with detailed experiments in two-core and four-core SMP benchmarks based on a RISC processor core.