A Totally Self-Checking Error Indicator
IEEE Transactions on Computers
On error indication for totally self-checking systems
IEEE Transactions on Computers
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
On the design of self-checking functional units based on Shannon circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
ISIS: A Fail-Safe Interface Realized in Smart Power Technology
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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This paper presents the design of strongly fail-safe interfaces which transform binary signals, generated by a system with error detection capabilities and eventually with fault-tolerant capabilities, into fail-safe signals, that is to say, into signals which, in the presence of failures, will be either correct or safe. The strongly fail-safe property is achieved by means of concurrent checking techniques. The interest of these interfaces is that they can be implemented in VLSI, while the conventional fail-safe interfaces require using discrete components. A formal theory of fail-safe systems is developed to guide the implementation of the new solutions