Arithmetic for an SVD processor
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Fundamentals of digital image processing
Fundamentals of digital image processing
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)
IEEE Transactions on Computers
An Angle Recording Method for CORDIC Algorithm Implementation
IEEE Transactions on Computers
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics
IEEE Transactions on Computers
An Introduction to Computer Graphics and Creative 3-D Environments
An Introduction to Computer Graphics and Creative 3-D Environments
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
Efficient CORDIC algorithms and architectures for low area and high throughput implementation
IEEE Transactions on Circuits and Systems II: Express Briefs
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture
IEEE Transactions on Circuits and Systems for Video Technology
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Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits. Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro-rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis for different Xilinx field-programmable gate-array platforms.