A Parallel Double-Step CORDIC Algorithm for Digital Down Converter
CNSR '09 Proceedings of the 2009 Seventh Annual Communication Networks and Services Research Conference
Efficient CORDIC algorithms and architectures for low area and high throughput implementation
IEEE Transactions on Circuits and Systems II: Express Briefs
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power and high-accurate synchronization for IEEE 802.16d systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
International Journal of Reconfigurable Computing
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence
Journal of Signal Processing Systems
Area-time efficient scaling-free CORDIC using generalized micro-rotation selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CORDIC designs for fixed angle of rotation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1/√2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm2 and its power dissipation is 7 mW in IHP in-house 0.25-μm BiCMOS technology.