Area-time efficient scaling-free CORDIC using generalized micro-rotation selection

Authors:
Supriya Aggarwal;Pramod K. Meher;Kavita Khare
Affiliations:
National Institute of Technology, Bhopal, India;Department of Embedded Systems, Institute of Infocomm Research, Singapore;National Institute of Technology, Bhopal, India
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 7
Cited 0

Parallel Compensation of Scale Factor for the CORDIC Algorithm

Journal of VLSI Signal Processing Systems
An Angle Recording Method for CORDIC Algorithm Implementation

IEEE Transactions on Computers
A Scale Factor Correction Scheme for the CORDIC Algorithm

IEEE Transactions on Computers
Efficient CORDIC algorithms and architectures for low area and high throughput implementation

IEEE Transactions on Circuits and Systems II: Express Briefs
50 years of CORDIC: algorithms, architectures, and applications

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Enhanced scaling-free CORDIC

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.