Theory of linear and integer programming
Theory of linear and integer programming
Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Dependence Analysis for Supercomputing
Dependence Analysis for Supercomputing
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
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We present a novel design of a bit-level matrix multiplier in which individual bits of a word do not have to be processed as a unit. In bit-level architectures the carry propagation delay is eliminated from the critical path. For example, in matrix multiplication, the carry chain of calculating the product of two numbers is broken by sending the partial sums and carries of the product to the accumulating operation instead of the whole finished word. In contrast, in a word-level matrix multiplier a product of two words has to be computed completely before it can be added to the next word-level product. Bit-level architectures for fixed-point matrix multiplication are proven to be O(logp) times faster than the corresponding word-level architecture, where p is the word length. The design is modified from our previous work to handle two's complement numbers as well. The design procedure is shown in detail by presenting the dependence graph, time and space mappings of our design. In addition, the time optimality and conflict-free properties of the design are also proven.