Implementations of square-root and exponential functions for large FPGAs

Authors:
Mariusz Bajger;Amos R. Omondi
Affiliations:
School of Informatics and Engineering, Flinders University, Bedford Park, SA, Australia;School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.