Improving Memory Traffic by Assembly-Level Exploitation of Reuses for Vector Registers
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I3D '01 Proceedings of the 2001 symposium on Interactive 3D graphics
Finite Precision Error Analysis of Neural Network Hardware Implementations
IEEE Transactions on Computers
Low-error, High-speed Approximation of the Sigmoid Function for Large FPGA Implementations
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ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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