Highly efficient, limited range multipliers for LUT-based FPGA architectures

Authors:
R. H. Turner;R. F. Woods
Affiliations:
Institute of Electronics, Communications and Information Technology, Queen's University of Belfast, Belfast, Northern Ireland;Institute of Electronics, Communications and Information Technology, Queen's University of Belfast, Belfast, Northern Ireland
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.