Efficient synthesis of distributed vector multipliers
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
Journal of VLSI Signal Processing Systems
A Fast Constant Coefficient Multiplier for the XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Highly efficient, limited range multipliers for LUT-based FPGA architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.