Communication-Centric SoC Debug Using Transactions

Authors:
Bart Vermeulen;Kees Goossens;Remco van Steeden;Martijn Bennebroek
Affiliations:
NXP Semiconductors Research, The Netherlands;NXP Semiconductors Research, The Netherlands/ Technical University Delft, The Netherlands;Technical University of Twente, The Netherlands;Philips Research, The Netherlands
Venue:
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Year:
2007

Citing 0
Cited 4

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Automated trace signals identification and state restoration for improving observability in post-silicon validation

Proceedings of the conference on Design, automation and test in Europe
An on-chip AHB bus tracer with real-time compression and dynamic multiresolution supports for SoC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

The growth in System-on-Chip complexity puts pressure on system verification. Due to limitations in the pre-silicon verification process, errors in hardware and software slip through to the stage when silicon and the complete software stack are first brought together. Finding the remaining errors at this stage is becoming increasing difficult. We propose that debugging should be communication-centric at first and based on transactions. We combine run-time, on-chip abstraction of system data to the transaction level, with system-level debug control over the communication infrastructure. We prove our concepts and architecture with a gate-level implementation that includes a Network-on- Chip, breakpoint monitors, clock and reset control (all programmable through an IEEE 1149.1 TAP), and give a quantification of the associated hardware cost.