Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Power supply noise can significantly impact the performance of deep submicron designs. Existing timing analysis techniques cannot capture the effects of power supply noise on the signal/cell delays. This is because these delay effects are highly input pattern dependent. Therefore, the predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a dynamic timing analysis technique that can take into account the impact of the power supply noise on the signal/cell propagation delays. Our technique is based on considering the input patterns that produce the worst-case power supply noise effects on the propagation delays of the longest true paths in the circuit. Our experimental results show that the circuit delay predicted by our dynamic timing analysis method is significantly longer than the delay predicted using traditional timing analysis tools.