Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Random walks in a supply network
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power-supply network optimization using multigrid-based technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitor planning with analytical delay model on RLC power grid
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) as the optimization engine, and partitioning scheme for dealing with large-sized circuits. We show that by directly optimizing the decoupling capacitor (decap) areas as the objective function and using the time-domain adjoint method, SLP can deliver much better quality in terms of decap budget than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for larger circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase.