Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 37th Annual Design Automation Conference
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip power-supply network optimization using multigrid-based technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
Integration, the VLSI Journal
Finding the worst voltage violation in multi-domain clock gated power network
Proceedings of the conference on Design, automation and test in Europe
Noise minimization during power-up stage for a multi-domain power network
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Predicting the worst-case voltage violation in a 3D power network
Proceedings of the 11th international workshop on System level interconnect prediction
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
On-chip power network optimization with decoupling capacitors and controlled-ESRs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hi-index | 0.00 |
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain adjoint method, SLP can deliver much better quality than existing methods based on the merged time-domain adjoint method. The partitioning strategy further improves the scalability of the proposed algorithm and makes it efficient for large circuits. The resulting algorithm is general enough for any P/G network. Experimental results demonstrate the advantage of the proposed method over existing state-of-the-art methods in terms of solution quality at a mild computation cost increase.