Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Noise minimization during power-up stage for a multi-domain power network
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Predicting the worst-case voltage violation in a 3D power network
Proceedings of the 11th international workshop on System level interconnect prediction
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This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (ILP) formulation is proposed to identify the worst-case gating pattern and the maximum variation area. The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results are also compared with a case where peak voltage variation is induced, which shows the latter technique largely underestimated the overall variation effect.