HiSIM: hierarchical interconnect-centric circuit simulator

Authors:
Tsung-Hao Chen;Jeng-Liang Tsai;T. Karnik
Affiliations:
Synopsis, Inc., Mountain View, CA, USA;Dept. of Comput. & Commun. Eng., Thessaly Univ., Volos, Greece;Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

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Abstract

To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to handle such a tremendous challenge in both efficiency and accuracy. We establish a solid framework that simultaneously takes advantage of a hierarchical nonlinear circuit simulation algorithm and an advanced large-scale linear circuit simulation method using a new predictor-corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect-centric circuit simulator, is capable of handling the post-layout RLKC power and signal integrity analysis task efficiently and accurately. Experimental results demonstrate over 180X speed up over the conventional flat simulation method with SPICE-level accuracy.