Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A zero-skew clock routing scheme for VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Zero skew clock routing in multiple-clock synchronous systems
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A buffer distribution algorithm for high-speed clock routing
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
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This paper presents a methodology for automatic generation of clock trees in an ASIC design at the schematic/netlist level. New algorithms and heuristics are described: they have been inserted with success in an industrial ASIC design flow, after the logic synthesis and optimization step. Our algorithms, by different heuristics, take particularly into account those elements connected as transmitter-receiver couples which represent the most critical configurations for circuit synchronization. Improvement of clock tree performance has also been obtained by means of an interaction strategy between logic and physical design phases.