Y.-M. Li;M. A. Jabri
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Automatic clock tree generation in ASIC designs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retiming: Theory and practice
Integration, the VLSI Journal