Optimal orientations of cells in slicing floorplan designs
Information and Control
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proceedings of the third international conference on Genetic algorithms
A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
Integration, the VLSI Journal
Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
A genetic algorithm for macro cell placement
EURO-DAC '92 Proceedings of the conference on European design automation
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Timing influenced general-cell genetic floorplanner
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
An optimal algorithm for area minimization of slicing floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms for Multiobjective Optimization: FormulationDiscussion and Generalization
Proceedings of the 5th International Conference on Genetic Algorithms
Genetic Algorithms Applied to the Physical Design of VLSI Circuits: A Survey
PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
T0 Engineering Data
| Hi-index | 0.01 |
A genetic algorithm for building-block placement of ICs and MCMs is presented that simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, 3-dimensional cost function and searching for a set of distinct solutions representing the best trade-offs of the cost dimensions. From the output solutions, the designer can choose the solution with the preferred trade-off. In contrast to existing approaches, the required properties of the output solutions are specified without using weights or bounds. Consequently, the practical problems of specifying these quantities are eliminated. Promising experimental results are obtained for various placement problems, including a real-world design. Solution sets representing good, balanced cost trade-offs are found using a reasonable amount of runtime. Furthermore, the performance is shown to be comparable to that of simulated annealing in the special case of 1-dimensional optimization, in which direct comparison is possible.