Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor

Authors:
Nevine Nassif;Madhav P. Desai;Dale H. Hall
Affiliations:
Digital Equipment Corportation, Hudson MA;Indian Institute of Technology, Mumbai, India;Digital Equipment Corportation, Hudson MA
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

Citing 2
Cited 4

A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Designing high performance CMOS microprocessors using full custom techniques

DAC '97 Proceedings of the 34th annual Design Automation Conference

RESTA: a robust and extendable symbolic timing analysis tool

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Performance benefits of monolithically stacked 3D-FPGA

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Journal of Signal Processing Systems
BDD decomposition for delay oriented pass transistor logic synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50% point delay of CMOS circuits in a static timing verifier. Elmore delays computed with these models fall within 10% of SPICE and can be computed thousands of times faster than if computed using SPICE. These models were used to verify critical paths during the design of a 600MHz microprocessor.