IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Critical paths in circuits with level-sensitive latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Computing logic-stage delays using circuit simulation and symbolic elmore analysis
Proceedings of the 38th annual Design Automation Conference
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
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Successful timing analysis for high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today's CPU designs make this difficult. A good circuit-level static timing analysis tool should 1) consider both internally or externally specified input constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. In this paper, we present RESTA, a Robust and Extendable Symbolic Timing Analysis tool that aims to address these three goals. RESTA estimates the delay for all valid input assignments, while naturally handling input constraints. We start with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation for the circuits without altering the symbolic algorithms. Our worst-case delay estimates are within 10% of SPICE for over 90% of the circuits we simulated.