Multilevel Factorization Technique for Pass Transistor Logic

Authors:
A. Jaekel;G. A. Jullien;S. Bandyopadhyay
Affiliations:
-;-;-
Venue:
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Year:
1996

Citing 1
Cited 1

Fundamentals of Computer Alori

Fundamentals of Computer Alori

Logic synthesis for large pass transistor circuits

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

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Abstract

Pass Transistor Logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks.