Design optimization of low-power 90nm CMOS SOC application using 0.5v bulk PMOS dynamic-threshold with dual threshold (MTCMOS): BP-DTMOS-DT technique

Authors:
Chih-Hsiang Lin;James B. Kuo
Affiliations:
Dept of Electrical Engineering, BL-528, National Taiwan University, Taipei, Taiwan;Dept of Electrical Engineering, BL-528, National Taiwan University, Taipei, Taiwan
Venue:
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

This paper reports a 0.5V bulk PMOS dynamic-threshold technique enhanced with dual threshold (MTCMOS): BP-DTMOS-DT for design optimization of low-power SOC application using 90nm multi-threshold CMOS technology. Via the HVT/BP-DTMOS-DT-type logic cell technique generated by the special gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, consuming 22% less static leakage power at the operating frequency of 400MHz as compared to the HVT/LVT-type counterpart optimized by the GDSPOM reported before.