Low-Power 32bit×32bit multiplier design with pipelined block-wise shutdown

Authors:
Yong-Ju Jang;Yoan Shin;Min-Cheol Hong;Jae-Kyung Wee;Seongsoo Lee
Affiliations:
School of Electronics Engineering, Soongsil University, Seoul, Korea;School of Electronics Engineering, Soongsil University, Seoul, Korea;School of Electronics Engineering, Soongsil University, Seoul, Korea;School of Electronics Engineering, Soongsil University, Seoul, Korea;School of Electronics Engineering, Soongsil University, Seoul, Korea
Venue:
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Year:
2005

Citing 6
Cited 2

Predictive system shutdown and other architectural techniques for energy efficient programmable computation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

DAC '98 Proceedings of the 35th annual Design Automation Conference
A survey of design techniques for system-level dynamic power management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Automated selective multi-threshold design for ultra-low standby applications

Proceedings of the 2002 international symposium on Low power electronics and design
Saving Power by Synthesizing Gated Clocks for Sequential Circuits

IEEE Design & Test
Microarchitectural dI/dt Control

IEEE Design & Test

Design of sensor signal processing algorithm and its SoC architecture for bio-sensor systems and intelligent robots

AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
Low-Power h.264 deblocking filter algorithm and its soc implementation

PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a novel low-power 32bit×32bit multiplier with pipelined block-wise shutdown scheme. When it idles, it turns off supply voltage to reduce both dynamic and static power. It shutdowns and wakes up sequentially along with pipeline stage to avoid power line noise. In idle mode, the proposed multiplier consumes 0.013mW and 0.006mW in 0.13μm and 0.09μm technologies, respectively, and it reduces power consumption to 0.07%~0.08% of active mode. As fabrication technology becomes small, power efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not. The low-power design methodology in this paper can be easily adopted in most functional blocks with pipeline architecture.