Design and integration methods for a multi-threaded dual core 65nm Xeon® processor

Authors:
Raj Varada;Mysore Sriram;Kris Chou;James Guzzo
Affiliations:
Intel Corporation, Santa Clara, CA;Intel Corporation, Santa Clara, CA;Intel Corporation, Santa Clara, CA;Intel Corporation, Santa Clara, CA
Venue:
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Year:
2006

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Abstract

The success of building a complex multi-billion transistor processor is very dependent on robust and silicon proven design and integration methods. The complexity of 65nm process and striving for best in class performance with aggressive time to market schedule put a heavy emphasis on innovative design and integration methods to enable working silicon. In this paper, we describe the design and integration methods successfully used in a multi-threaded dual core 65nm Xeon® Processor. Index Terms---Design Methods; Integration; processor; Xeon®.