Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Fine-grain Priority Scheduling on Multi-channel Memory Systems
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
Handling the problems and opportunities posed by multiple on-chip memory controllers
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Proceedings of the Conference on Design, Automation and Test in Europe
A case for multi-channel memories in video recording
Proceedings of the Conference on Design, Automation and Test in Europe
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture
CHINAGRID '11 Proceedings of the 2011 Sixth Annual ChinaGrid Conference
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Proceedings of the 49th Annual Design Automation Conference
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Optimal utilization of a multi-channel memory, such as Wide IO DRAM, as shared memory in multi-processor platforms depends on the mapping of memory clients to the memory channels, the granularity at which the memory requests are interleaved in each channel, and the bandwidth and memory capacity allocated to each memory client in each channel. Firm real-time applications in such platforms impose strict requirements on shared memory bandwidth and latency, which must be guaranteed at design-time to reduce verification effort. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multi-channel memories in real-time systems. This paper has four key contributions: (1) A real-time multi-channel memory controller architecture with a new programmable Multi-Channel Interleaver unit. (2) A novel method for logical-to-physical address translation that enables interleaving memory requests across multiple memory channels at different granularities. (3) An optimal algorithm based on an Integer Linear Program (ILP) formulation to map memory clients to memory channels considering their communication dependencies, and to configure the memory controller for minimum bandwidth utilization. (4) We experimentally evaluate the run-time of the algorithm and show that an optimal solution can be found within 15 minutes for realistically sized problems. We also demonstrate configuring a multi-channel Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the effectiveness of our approach.