Dataflow models for shared memory access latency analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
ACM SIGBED Review - Special Issue on the Work-in-Progress (WIP) Session at the 2009 IEEE Real-Time Systems Symposium (RTSS)
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Conservative open-page policy for mixed time-criticality memory controllers
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture and optimal configuration of a real-time multi-channel memory controller
Proceedings of the Conference on Design, Automation and Test in Europe
Memory-map selection for firm real-time SDRAM controllers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
In shared-memory multi-processor Systems on Chip for media processing, the access to off-chip memory is often a critical resource. The memory channel is shared by a mix of streams with timing requirements at different levels. The streams are arbitrated in the memory access network. Some streams have to meet a hard deadline for each transaction; other streams have to meet task-level execution-time constraints, where task execution times depend on the service received when performing memory accesses. Earlier work has resulted in arbitration algorithms that provide the necessary balance between the different stream types, allowing aggressive system design with a high utilization of the memory access path. The next challenge is to provide real-time analysis in an early stage of system design. To address this challenge, this paper proposes a practical approach that combines proven analytical methods with fast simulations. The approach provides a design space from which to choose arbiter settings and buffer sizes for memory-communication buffers.