Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Classification and Analysis of Predictable Memory Patterns
RTCSA '10 Proceedings of the 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic Generation of Efficient Predictable Memory Patterns
RTCSA '11 Proceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 01
Improved Power Modeling of DDR SDRAMs
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Conservative open-page policy for mixed time-criticality memory controllers
Proceedings of the Conference on Design, Automation and Test in Europe
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A reconfigurable real-time SDRAM controller for mixed time-criticality systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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A modern real-time embedded system must support multiple concurrently running applications. To reduce costs, critical SoC components like SDRAM memories are often shared between applications with a variety of firm real-time requirements. To guarantee that the system works as intended, the memory controller must be configured such that all the real-time requirements of all sharing applications are satisfied. The attainable worst-case bandwidth, latency, and power of the memory depend largely on memory map configuration. Sharing SDRAM amongst multiple applications is challenging, since their requirements might call for different memory maps. This paper presents an exploration of the memory-map design space. Two contributions improve the memory-map selection procedure. The first contribution reduces the minimum access granularity by interleaving requests over a configurable number of banks instead of all banks. This technique is beneficial for worst-case performance in terms of bandwidth, latency and power. As a second contribution, we present a methodology to derive a memory-map configuration, i.e. the access granularity and number of interleaved banks, from a specification of the real-time application requirements and an overall memory power budget.