A General Model for Recurring Real-Time Tasks
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
Roofline: an insightful visual performance model for multicore architectures
Communications of the ACM - A Direct Path to Dependable Software
High-Performance Embedded Architecture and Compilation Roadmap
Transactions on High-Performance Embedded Architectures and Compilers I
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).