Architecture and optimal configuration of a real-time multi-channel memory controller
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
With more data-intensive applications appearing in the present social life, the NAND flash memory acting as a replacement candidate of hard disk drives is popularly used in some data centers due to its lower power consumption, faster random access, and higher shock resistance. But the traditional solid state disk exposes the limitation of bandwidth. To this end, we deliver the scalable multi-channel flash memory controller architecture in this paper to exploit the parallelism of multiple chips. It supports all the flash operations, and boosts the performance by evenly distributing multiple accesses among different chips when using the error correction code to improve its reliability. The functions of the multi-channel parallel controller are validated according to a wide spread of workloads. And the evaluation results show that our proposed eight-channel controller outperforms the traditional controller by more than three times and can be well scaled to be 128 channels without extra critical timing path.