An educational tool for testing hierarchical multilevel caches
ACM SIGARCH Computer Architecture News
Utilizing reuse information in data cache management
ICS '98 Proceedings of the 12th international conference on Supercomputing
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CacheSim: a cache simulator for teaching memory hierarchy behaviour
ITiCSE '99 Proceedings of the 4th annual SIGCSE/SIGCUE ITiCSE conference on Innovation and technology in computer science education
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Storage Management Programmable Process
Storage Management Programmable Process
Splitting the Data Cache: A Survey
IEEE Concurrency
Computer
mlcache: A Flexible Multi-Lateral Cache Simulator
MASCOTS '98 Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Efficient memory simulation in SimICS
SS '95 Proceedings of the 28th Annual Simulation Symposium
CAMERA: introducing memory concepts via visualization
Proceedings of the 36th SIGCSE technical symposium on Computer science education
Understanding cache hierarchy interactions with a program-driven simulator
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
SlackSim: a platform for parallel simulations of CMPs on CMPs
ACM SIGARCH Computer Architecture News
Evaluation techniques for storage hierarchies
IBM Systems Journal
Location cache design and performance analysis for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM SIGARCH Computer Architecture News
Transformer: a functional-driven cycle-accurate multicore simulator
Proceedings of the 49th Annual Design Automation Conference
Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises
IEEE Transactions on Education
Importance of Coherence Protocols with Network Applications on Multicore Processors
IEEE Transactions on Computers
| Hi-index | 0.00 |
This paper presents XMSIM, an early memory hierarchy evaluation simulator for multimedia applications. The input is source code in C and a memory hierarchy description and the output is profiling information about memory operations during the execution of the source code. A memory hierarchy can be made of arbitrary levels of cache and main memory while multiple hierarchies can be modeled in parallel. Any subset of the source code's variables can be mapped to the simulated memory units to any location of choice and the contents of any memory level are available at any execution step. Specialized routines can be added to verify correctness of optimizations made in the source code in respect to memory usage. The simulator is extensible in that additional memory characteristics can be modeled and more information on the effect of software-hardware interaction can be extended. A demonstration is presented of how the tool can be used to optimize a multimedia application.