Talisman: fast and accurate multicomputer simulation
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Embra: fast and flexible machine simulation
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Using the SimOS machine simulator to study complex computer systems
ACM Transactions on Modeling and Computer Simulation (TOMACS)
An evaluation of Penny: a system for fine grain implicit parallelism
PASCO '97 Proceedings of the second international symposium on Parallel symbolic computation
Efficient instruction cache simulation and execution profiling with a threaded-code interpreter
Proceedings of the 29th conference on Winter simulation
Trace Factory: Generating Workloads for Trace-Driven Simulation of Shared-Bus Multiprocessors
IEEE Parallel & Distributed Technology: Systems & Technology
A Study of the Efficiency of Shared Attraction Memories in Cluster-Based COMA Multiprocessors
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
A Simulation Tool for Evaluating Shared Memory Systems
ANSS '03 Proceedings of the 36th annual symposium on Simulation
Simulation as a tool for optimizing memory accesses on NUMA machines
Performance Evaluation - Performance modelling and evaluation of high-performance parallel and distributed systems
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
valuetools '06 Proceedings of the 1st international conference on Performance evaluation methodolgies and tools
Design and Implementation of aWorkload Specific Simulator
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
Operating system support for virtual machines
ATEC '03 Proceedings of the annual conference on USENIX Annual Technical Conference
SimICS/sun4m: a virtual workstation
ATEC '98 Proceedings of the annual conference on USENIX Annual Technical Conference
Accurate and scalable simulation of network of heterogeneous sensor devices
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
An Interactive Graphical Environment for Code Optimization
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part II
CMP Cache Architecture and the OpenMP Performance
IWOMP '07 Proceedings of the 3rd international workshop on OpenMP: A Practical Programming Model for the Multi-Core Era
Performance advantage of reconfigurable cache design on multicore processor systems
International Journal of Parallel Programming
Dynamic binary translation specialized for embedded systems
Proceedings of the 6th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments
COREMU: a scalable and portable parallel full-system emulator
Proceedings of the 16th ACM symposium on Principles and practice of parallel programming
CacheIn: a toolset for comprehensive cache inspection
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part II
Comprehensive cache inspection with hardware monitors
PaCT'05 Proceedings of the 8th international conference on Parallel Computing Technologies
An early memory hierarchy evaluation simulator for multimedia applications
Microprocessors & Microsystems
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We describe novel techniques used for efficient simulation of memory in SimICS; an instruction level simulator developed at SICS. The design has focused on efficiently supporting the simulation of multiprocessors, analyzing complex memory hierarchies and running large binaries with a mixture of system level and user level code. A software caching mechanism (the Simulator Translation Cache, STC) improves the performance of interpreted memory operations by reducing the number of calls to complex memory simulation code. Major data structures are allocated lazily to reduce the size of the simulator process. A well defined internal interface to generic memory simulation simplifies user extensions. Leveraging on a flexible interpreter based on threaded code allows runtime selection of statistics gathering, memory profiling, and cache simulation with low overhead. The result is a memory simulation scheme that supports a range of features for use in computer architecture research, program profiling, and debugging.