The POWER2 performance monitor
IBM Journal of Research and Development
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Automated cache optimizations using CME driven diagnosis
Proceedings of the 14th international conference on Supercomputing
SIP: Performance Tuning through Source Code Interdependence
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
A Simulation Tool for Evaluating Shared Memory Systems
ANSS '03 Proceedings of the 36th annual symposium on Simulation
Efficient memory simulation in SimICS
SS '95 Proceedings of the 28th Annual Simulation Symposium
A Portable Programming Interface for Performance Evaluation on Modern Processors
International Journal of High Performance Computing Applications
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Computer systems usually rely on hardware counters and software instrumentation to acquire performance information about the cache access behavior. These approaches either provide only limited data or are restricted in their applicability. This paper introduces a novel approach based on a hardware cache monitoring facility that exhibits both the details of traditional software mechanisms and the low–overhead of hardware counters. More specially, the cache monitor can be combined with any location of the memory hierarchy and present a detailed view of the complete memory access behavior of applications. The monitoring concept has been verified using a multiprocessor simulator. Initial experimental results show its feasibility in terms of hardware design and functionality with respect to providing comprehensive performance data.