Performance advantage of reconfigurable cache design on multicore processor systems

  • Authors:

  • Jie Tao;Marcel Kunze;Fabian Nowak;Rainer Buchty;Wolfgang Karl

  • Affiliations:

  • Department of Computer Science and Technology, Jilin University, Changchun, Jilin, People's Republic of China and Steinbuch Centre for Computing, Forschungszentrum Karlsruhe, Karlsruhe Institute o ...;Steinbuch Centre for Computing, Forschungszentrum Karlsruhe, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institut für Technische Informatik, Universität Karlsruhe, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institut für Technische Informatik, Universitä Karlsruhe, Karlsruhe Institute of Technology, Karlsruhe, Germany;Institut für Technische Informatik, Universitä Karlsruhe, Karlsruhe Institute of Technology, Karlsruhe, Germany

  • Venue:
  • International Journal of Parallel Programming
  • Year:
  • 2008

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Abstract

With the trends of microprocessor design towards multicore, cache performance becomes more important because an off-chip access would be increasingly expensive due to the competition across the processor cores. A question arises: How to design the cache architecture to prevent a performance bottleneck caused by data accesses? This work studies a reconfigurable cache architecture that can be dynamically configured for meeting the individual demand of running applications. Using a self-developed cache simulator, we first examined how different cache organization and configuration influence the parallel execution of OpenMP applications. The experimental results show that applications benefit from a flexible cache with reconfigurability. This motivated us to go a step further and develop a hardware prototype of this novel architecture.