CMP Cache Architecture and the OpenMP Performance

Authors:
Jie Tao;Kim D. Hoàng;Wolfgang Karl
Affiliations:
Department of Computer Science and Technology, Jilin University, P.R. China and Institut für wissenschaftliches Rechnen, Forschungszentrum Karlsruhe GmbH, Karlsruhe, 76021;Institut für Technische Informatik, Universität Karlsruhe (TH), Karlsruhe, Germany 76128;Institut für Technische Informatik, Universität Karlsruhe (TH), Karlsruhe, Germany 76128
Venue:
IWOMP '07 Proceedings of the 3rd international workshop on OpenMP: A Practical Programming Model for the Multi-Core Era
Year:
2007

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Abstract

Chip-multiprocessor (CMP) is regarded as the next generation of microprocessor architectures. For programming such machines OpenMP, a standard shared memory model, is a challenging candidate. A question arises: How to design the CMP hardware for high performance of OpenMP applications?This work explores the answer with cache architecture as a case study. Based on a simulator, we investigate how cache organization and reconfigurability influence the parallel execution of an OpenMP program. The achieved results can direct both architecture developers to determine hardware design and the programmers to generate efficient codes.