Sustainable multi-core architecture with on-chip wireless links

Authors:
Jacob Murray;John Klingner;Partha P. Pande;Behrooz Shirazi
Affiliations:
Washington State University, Pullman, USA;Cornell College, Mount Vernon, USA;Washington State University, Pullman, USA;Washington State University, Pullman, USA
Venue:
Proceedings of the great lakes symposium on VLSI
Year:
2012

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Abstract

Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.