Using virtual lines to enhance locality exploitation

Authors:
O. Temam;Y. Jegou
Affiliations:
University of Versailles, 78000 Versailles, France;IRISA, 35042 Rennes Cedex, France
Venue:
ICS '94 Proceedings of the 8th international conference on Supercomputing
Year:
1994

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Abstract

Because the spatial locality of numerical codes is significant, the potential for performance improvements is important. However, large cache lines cannot be used in current on-chip data caches because of the important pollution they breed. In this paper, we propose a hardware design, called the Virtual Line Scheme, that allows the utilization of large virtual cache lines when fetching data from memory for better exploitation of spatial locality, while the actual physical cache line is smaller than currently found cache lines for better exploitation of temporal locality. Simulations show that a 17% to 64% reduction of the average memory access time can be obtained for a 20-cycle memory latency. It is also shown how simple software informations can be used to significantly decrease memory traffic, a flaw associated with the utilization of large cache lines.