Designing High-Performance Processors Using Real Address Prediction

Authors:
K. A. Hua;L. A. Liu;J. Peir
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
1993

Citing 6
Cited 1

An in-cache address translation mechanism

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Cache design of a sub-micron CMOS system/370

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Coherency for multiprocessor virtual address caches

ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Virtual Memory

ACM Computing Surveys (CSUR)
Cache Memories

ACM Computing Surveys (CSUR)

Improving cache performance with balanced tag and data paths

Proceedings of the seventh international conference on Architectural support for programming languages and operating systems

Quantified Score

Hi-index	14.98

Visualization

Abstract

The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe.