Tile size selection using cache organization and data layout

  • Authors:

  • Stephanie Coleman;Kathryn S. McKinley

  • Affiliations:

  • Intermetrics, Inc., 733 Concord Ave., Cambridge, MA;Computer Science, LGRC, University of Massachusetts, Amherst, MA

  • Venue:
  • PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
  • Year:
  • 1995

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Abstract

When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for choosing problem-size dependent tile sizes based on the cache size and cache line size for a direct-mapped cache. The algorithm eliminates both capacity and self-interference misses and reduces cross-interference misses. We measured simulated miss rates and execution times for our algorithm and two others on a variety of problem sizes and cache organizations. At higher set associativity, our algorithm does not always achieve the best performance. However on direct-mapped caches, our algorithm improves simulated miss rates and measured execution times when compared with previous work.