Parametric multi-level tiling of imperfectly nested loops

  • Authors:

  • Albert Hartono;Muthu Manikandan Baskaran;Cédric Bastoul;Albert Cohen;Sriram Krishnamoorthy;Boyana Norris;J. Ramanujam;P. Sadayappan

  • Affiliations:

  • The Ohio State University, Columbus, OH, USA;The Ohio State University, Columbus, OH, USA;Paris-Sud 11 University and HiPEAC Network, Orsay, France;INRIA Saclay and HiPEAC Network, Orsay, France;Pacific Northwest National Laboratory, Richland, WA, USA;Argonne National Laboratory, Argonne, IL, USA;Louisiana State University, Baton Rouge, LA, USA;The Ohio State University, Columbus, OH, USA

  • Venue:
  • Proceedings of the 23rd international conference on Supercomputing
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multi-level tiled code is essential for maximizing data reuse in systems with deep memory hierarchies. Tiled loops with parametric tile sizes (not compile-time constants) facilitate runtime feedback and dynamic optimizations used in iterative compilation and automatic tuning. Previous parametric multi-level tiling approaches have been restricted to perfectly nested loops, where all assignment statements are contained inside the innermost loop of a loop nest. Previous solutions to tiling for imperfect loop nests have only handled fixed tile sizes. In this paper, we present an approach to parametric multi-level tiling of imperfectly nested loops. The tiling technique generates loops that iterate over full rectangular tiles, making them amenable to compiler optimizations such as register tiling. Experimental results using a number of computational benchmarks demonstrate the effectiveness of the developed tiling approach.