Multi-level tiling: M for the price of one

  • Authors:

  • DaeGon Kim;Lakshminarayanan Renganarayanan;Dave Rostron;Sanjay Rajopadhye;Michelle Mills Strout

  • Affiliations:

  • Colorado State University, Fort Collins, Colorado;Colorado State University, Fort Collins, Colorado;Colorado State University, Fort Collins, Colorado;Colorado State University, Fort Collins, Colorado;Colorado State University, Fort Collins, Colorado

  • Venue:
  • Proceedings of the 2007 ACM/IEEE conference on Supercomputing
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. High-performance implementations use multiple levels of tiling to exploit the hierarchy of parallelism and cache/register locality. Efficient generation of multi-level tiled code is essential for effective use of multi-level tiling. Parameterized tiled code, where tile sizes are not fixed but left as symbolic parameters can enable several dynamic and run-time optimizations. Previous solutions to multi-level tiled loop generation are limited to the case where tile sizes are fixed at compile time. We present an algorithm that can generate multi-level parameterized tiled loops at the same cost as generating single-level tiled loops. The efficiency of our method is demonstrated on several benchmarks. We also present a method-useful in register tiling-for separating partial and full tiles at any arbitrary level of tiling. The code generator we have implemented is available as an open source tool.