Efficient tiled loop generation: D-tiling

  • Authors:

  • DaeGon Kim;Sanjay Rajopadhye

  • Affiliations:

  • Colorado State University, Fort Collins, CO, U.S.A.;Colorado State University, Fort Collins, CO, U.S.A.

  • Venue:
  • LCPC'09 Proceedings of the 22nd international conference on Languages and Compilers for Parallel Computing
  • Year:
  • 2009

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Abstract

Tiling is an important loop optimization for exposing coarse-grained parallelism and enhancing data locality. Tiled loop generation from an arbitrarily shaped polyhedron is a well studied problem. Except for the special case of a rectangular iteration space, the tiled loop generation problem has been long believed to require heavy machinery such as Fourier-Motzkin elimination and projection, and hence to have an exponential complexity. In this paper we propose a simple and efficient tiled loop generation technique similar to that for a rectangular iteration space. In our technique, each loop bound is adjusted only once, syntactically and independently. Therefore, our algorithm runs linearly with the number of loop bounds. Despite its simplicity, we retain several advantages of recent tiled code generation schemes—unified generation for fixed, parameterized and hybrid tiled loops, scalability for multi-level tiled loop generation with the ability to separate full tiles at any levels, and compact code. We also explore various schemes for multi-level tiled loop generation. We formally prove the correctness of our scheme and experimentally validate that the efficiency of our technique is comparable to existing parameterized tiled loop generation approaches. Our experimental results also show that multi-level tiled loop generation schemes have an impact on performance of generated code. The fact that our scheme can be implemented without sophisticated machinery makes it well suited for autotuners and production compilers.